Multi-tasking with Multiple Processors

A typical multi-processor environment is comprised of multiple microprocessors that share a common memory. Each processor also has its own private memory area for its own code and data. The main reason for using multiple processors is to increase power for a specific application, and therefore, the processors generally need to communicate with one another, and this is typically done through shared RAM.

Interprocessor Communication

There are various ways to handle inter-processor communication; the following is one approach. In the following discussion, sender means the processor (CPU) sending the message, and receiver means the processor (CPU) that will receive the message.

Sending a Message

Any processor may send a block of data (message) to another processor. A 256 byte shared RAM memory block (message area) is reserved for each processor. A message is sent to a processor by writing the message into the receiver's message area and then signaling the receiver that a message is waiting.

 

Message Collisions

Messages can collide when 2 or more processors send a message to the same receiver at the same time, which can result in over-written or interleaved messages. Note that a flag in shared RAM will not solve the collision problem, since after one processor reads the flag, another processor can read the flag on the next shared RAM bus cycle and, if the flag was 0, both processors will write a 1 into the flag and believe that they have exclusive access to the receiver's message area. Nor is the problem solved by a read-modify-write instruction like the 80x86 XCHG instruction, since although the instruction is indivisible for the processor that executes it, it is not indivisible with respect to the shared RAM data bus. For example, following the read portion of the XCHG instruction for processor A, processor B can read the same shared RAM word on the next bus cycle, before the processor A's XCHG instruction can write out the new value. This problem can be solved by preceding the XCHG instruction with a LOCK instruction, which asserts the 80x86 LOCK* pin, and designing the shared RAM data bus arbitration logic to incorporate the LOCK* pin so that other processors cannot access the shared RAM data bus while the LOCK* pin is asserted. Note that newer processors like the 80386 incorporate the LOCK implicitly into the XCHG instruction so the LOCK instruction is unnecessary.

Message Area Format

Each processor is assigned a specific area of shared RAM called the message area. The format is as follows.

word 0 (Semaphore)

Before writing into the message area, the sender must acquire the semaphore using the XCHG instruction, as outlined above.

 

word 1 (msgFlag)

The sender sets this flag to 1 when it has finished writing the message into the message area.

 

word 2 through 255 (msgBuffer)

This area contains the message.

Inter-processor Communication Protocol

The sender sends a message as follows.

1. The sender acquires the receiver's semaphore using the XCHG instruction as outlined above.
2. The sender writes the message into the receiver's message buffer.
3. The sender sets the receiver's msgFlag to 1 to indicate that the message is available.

A message is received by the receiver as follows.

1. The receiver waits for msgFlag to become 1.
2. The receiver copies the message from the message buffer to local memory.
3. The receiver clears msgFlag.
4. The receiver clears its semaphore, indicating that it is available to process another message.

Inter-task Communication Across Different Processors

The scheme above can be used to allow tasks on different processors to communicate with each other. Each processor requires an inter-processor send manager task (IPSM) and an inter-processor receive manager (IPRM) task. When a task sends a message to a task on a different physical processor, it must specify the receiver processor name and the receiver task name. The IPRM would periodically check for a message in shared RAM. When a message is detected the IPRM copies the message out of shared RAM and routes it to the destination task.

Concluding Remarks

The above is lacking in detail and there are other areas for discussion. For complete details, or information on how to obtain Tics 3.0 which incorporates inter-processor communications, please email us at Mike@TicsRealtime.com.

 

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